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86B
CY7C1386B CY7C1387B
512K x 36/1M x 18 Pipelined DCD SRAM
Features
* * * * * * * * * * * * * * * * Fast clock speed: 200, 167, 150, 133 MHz Provide high-performance 3-1-1-1 access rate Fast OE access times: 3.0, 3.4, 3.8, and 4.2 ns Optimal for depth expansion 3.3V (-5% / +10%) power supply Common data inputs and data outputs Byte Write Enable and Global Write control Double-cycle deselect Chip enable for address pipeline Address, data, and control registers Internally self-timed Write cycle Burst control pins (interleaved or linear burst sequence) Automatic power-down available using ZZ mode or CE deselect High-density, high-speed packages JTAG boundary scan for BGA packaging version Automatic power down available using ZZ mode or CE deselect registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, data inputs, address-pipelining Chip Enables (CEs), burst control inputs (ADSC, ADSP, and ADV), Write Enables (BWa, BWb, BWc, BWd and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and burst mode control (MODE). DQa,b,c,d and DPa,b,c,d apply to CY7C1386B and DQa,b and DPa,b apply to CY7C1387B. a, b, c, and d each are 8 bits wide in the case of DQ and 1 bit wide in the case of DP. Addresses and chip enables are registered with either Address Status Processor (ADSP) or Address Status Controller (ADSC) input pins. Subsequent burst addresses can be internally generated as controlled by the Burst Advance Pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate self-timed Write cycles. Write cycles can be one to four bytes wide as controlled by the write control inputs. Individual byte write allows individual byte to be written. BWa controls DQa and DQPa. BWb controls DQb and DQPb. BWc controls DQc and DQPd. BWd controls DQd-DQd and DQPd. BWa, BWb, BWc, and BWd can be active only with BWE LOW. GW LOW causes all bytes to be written. Write pass-through capability allows written data available at the output for the immediately next Read cycle. This device also incorporates pipelined enable circuit for easy depth expansion without penalizing system performance. The CY7C1386B and CY7C1387B are both double-cycle deselect parts. All inputs and outputs of the CY7C1386B and the CY7C1387B are JEDEC-standard JESD8-5-compatible.
Functional Description
The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced single-layer polysilicon, triple-layer metal technology. Each memory cell consists of six transistors. The CY7C1386B and CY7C1387B SRAMs integrate 524,288 x 36 and 1,048,576 x 18 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by
Selection Guide
200 MHz Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 3 315 20 167 MHz 3.4 285 20 150 MHz 3.8 265 20 133 MHz 4.2 245 20 Unit ns mA mA
Cypress Semiconductor Corporation Document #: 38-05195 Rev. **
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CA 95134 * 408-943-2600 Revised December 3, 2001
CY7C1386B CY7C1387B
Logic Block Diagram CY7C1386B -- 512K x 36
MODE (A[1;0]) 2 CLK ADV ADSC ADSP A[18:0] GW BWE BW d BWc D BWb D BWa CE1 CE2 CE3 D BURST Q0 CE COUNTER Q1 CLR Q 19 17 D ADDRESS CE REGISTER D DQd, DPd BYTEWRITE REGISTERS DQc, DPc BYTEWRITE REGISTERS DQb, DPb BYTEWRITE REGISTERS DQa, DP a BYTEWRITE REGISTERS ENABLE CE REGISTER Q 17 19
512K x 36 MEMORY ARRAY
D
Q
Q
Q 36 Q 36
D ENABLE DELAY Q REGISTER OE ZZ SLEEP CONTROL
OUTPUT REGISTERS CLK
INPUT REGISTERS CLK
DQa,b,c,d DPa,b,c,d
Logic Block Diagram CY7C1387B -- 1M x 18
MODE (A[1;0]) 2 CLK ADV ADSC ADSP A[19:0] GW BWE BW b BWa BURST Q0 CE COUNTER Q1 CLR Q 19 17 D ADDRESS CE REGISTER D DQb, DPb BYTEWRITE REGISTERS DQa, DPa BYTEWRITE REGISTERS Q 17 19
1M x 18 MEMORY ARRAY
D
Q
CE1 CE2 CE3
18 D ENABLE CE CE REGISTER Q
18
D ENABLE DELAY Q REGISTER OE ZZ SLEEP CONTROL
OUTPUT REGISTERS CLK
INPUT REGISTERS CLK
DQa,b DPa,b
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CY7C1386B CY7C1387B
Pin Configurations
100-Pin TQFP (Top View)
A A CE1 CE2 BWd BWc BWb BWa CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A A A CE1 CE2 NC NC BWb BWa CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A DQPb NC NC DQb NC DQb VDDQ VDDQ VSSQ VSSQ NC DQb NC DQb DQb DQb DQb DQb VSSQ VSSQ VDDQ VDDQ DQb DQb DQb DQb NC VSS VDD NC NC VDD VSS ZZ DQa DQb DQa DQb VDDQ VDDQ VSSQ VSSQ DQa DQb DQa DQb DQa DPb NC DQa VSSQ VSSQ VDDQ VDDQ NC DQa NC DQa DQPa NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
DQPc DQc DQc VDDQ VSSQ DQc DQc DQc DQc VSSQ VDDQ DQc DQc NC VDD NC VSS DQd DQd VDDQ VSSQ DQd DQd DQd DQd VSSQ VDDQ DQd DQd DQPd
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
CY7C1386B (512K x 36)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
CY7C1387B (1M x 18)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
A NC NC VDDQ VSSQ NC DPa DQa DQa VSSQ VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSSQ DQa DQa NC NC VSSQ VDDQ NC NC NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MODE A A A A A1 A0 NC NC VSS VDD A A A A A A A A A
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MODE A A A A A1 A0 NC NC VSS VDD A A A A A A A A A
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
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CY7C1386B CY7C1387B
Pin Configurations (continued)
119-Ball BGA -- Top View CY7C1386B (512K x 36) 1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQc DQc VDDQ DQc DQc VDDQ DQd DQd VDDQ DQd DQd NC NC VDDQ 2 A A A DQPc DQc DQc DQc DQc VDD DQd DQd DQd DQd DQPd A 64M TMS 3 A A A VSS VSS VSS BWc VSS NC VSS BWd VSS VSS VSS MODE A TDI 4 ADSP ADSC VDD NC CE1 OE ADV GW VDD CLK NC BWE A1 A0 VDD A TCK 5 A A A VSS VSS VSS BWb VSS NC VSS BWa VSS VSS VSS VDD A TDO 6 A A A DQPb DQb DQb DQb DQb VDD DQa DQa DQa DQa DQPa A 32M NC 7 VDDQ NC NC DQb DQb VDDQ DQb DQb VDDQ DQa DQa VDDQ DQa DQa NC ZZ VDDQ
CY7C1387B (1M x 18) 1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQb NC VDDQ NC DQb VDDQ NC DQb VDDQ DQb NC NC 64M VDDQ 2 A A A NC DQb NC DQb NC VDD DQb NC DQb NC DQPb A A TMS 3 A A A VSS VSS VSS BWb VSS NC VSS VSS VSS VSS VSS MODE A TDI 4 ADSP ADSC VDD NC CE1 OE ADV GW VDD CLK NC BWE A1 A0 VDD 32M TCK 5 A A A VSS VSS VSS VSS VSS NC VSS BWa VSS VSS VSS VDD A TDO 6 A A A DQPa NC DQa NC DQa VDD NC DQa NC DQa NC A A NC 7 VDDQ NC NC NC DQa VDDQ DQa NC VDDQ DQa NC VDDQ NC DQa NC ZZ VDDQ
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CY7C1386B CY7C1387B
Pin Configurations (continued)
165-Ball Bump FBGA
CY7C1386B (512K x 36) -- 11 x 15 FBGA
1 A B C D E F G H J K L M N P R
NC NC DPc DQc DQc DQc DQc NC DQd DQd DQd DQd DPd NC MODE
2
A A NC DQc DQc DQc DQc VSS DQd DQd DQd DQd NC 64M 32M
3
CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A
4
BWc BWd VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A
5
BWb BWa VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS
6
CE3 CLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A A1 A0
7
BWE GW VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK
8
ADSC OE VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A
9
ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A
10
A A NC DQb DQb DQb DQb NC DQa DQa DQa DQa NC A A
11
NC 128M DPb DQb DQb DQb DQb ZZ DQa DQa DQa DQa DPa A A
CY7C1387B (1M x 18) -- 11 x 15 FBGA
1 A B C D E F G H J K L M N P R
NC NC NC NC NC NC NC NC DQb DQb DQb DQb DPb NC MODE
2
A A NC DQb DQb DQb DQb VSS NC NC NC NC NC 64M 32M
3
CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A
4
BWb NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A
5
NC BWa VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS
6
CE3 CLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A A1 A0
7
BWE GW VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK
8
ADSC OE VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A
9
ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A
10
A A NC NC NC NC NC NC DQa DQa DQa DQa NC A A
11
A 128M DPa DQa DQa DQa DQa ZZ NC NC NC NC NC A A
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CY7C1386B CY7C1387B
Pin Definitions
Name A0 A1 A BWa BWb BWc BWd GW I/O InputSynchronous InputSynchronous Description Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feeds the 2-bit counter. Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK.
InputSynchronous InputSynchronous Input-Clock
Global Write Enable input, active LOW. When asserted LOW on the rising edge of CLK, a global Write is conducted (ALL bytes are written, regardless of the values on BWa,b,c,d and BWE). Byte Write Enable input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write. Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW during a burst operation. Chip Enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. Chip Enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device (TQFP only). Chip Enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device (TQFP only). Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. Advance Input signal, sampled on the rising edge of CLK. When asserted, it automatically increments the address in a burst cycle. Address Strobe from Processor, sampled on the rising edge of CLK. When asserted LOW, A is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. Address Strobe from Controller, sampled on the rising edge of CLK. When asserted LOW, A[x:0] is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDDQ or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. ZZ "sleep" input. This active HIGH input places the device in a non-time critical "sleep" condition with data integrity preserved. Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by AX during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQx and DPx are placed in a three-state condition.DQ a,b,c and d are 8 bits wide. DP a,b,c and d are 1 bit wide.
BWE CLK
CE1
InputSynchronous InputSynchronous InputSynchronous InputAsynchronous
CE2 CE3 OE
ADV ADSP
InputSynchronous InputSynchronous
ADSC
InputSynchronous
MODE
Input-Pin
ZZ DQa, DPa DQb, DPb DQc, DPc DQd, DPd
InputAsynchronous I/OSynchronous
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CY7C1386B CY7C1387B
Pin Definitions
Name TDO TDI TMS TCK VDD VSS VDDQ VSSQ NC 32M 64M 128M I/O JTAG serial output synchronous JTAG serial input synchronous Test Mode Select synchronous JTAG serial clock Power supply Ground I/O Power Supply I/O Ground - - Description Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK (BGA only). Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK (BGA only). This pin controls the Test Access Port (TAP) state machine. Sampled on the rising edge of TCK (BGA only). Serial clock to the JTAG circuit (BGA only). Power supply inputs to the core of the device. Should be connected to 3.3V -5% +10% power supply. Ground for the core of the device. Should be connected to ground of the system. Power supply for the I/O circuitry. Should be connected to a 2.5V -5% or a 3.3V -5% +10% power supply (see page 20). Ground for the I/O circuitry. Should be connected to ground of the system. No connects. Pins are not internally connected. No connects. Reserved for address expansion. Pins are not internally connected.
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CY7C1386B CY7C1387B
Introduction
Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 4.2 ns (133-MHz device). The CY7C1386B/ supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium(R) and i486 processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BWa,b,c,d for 1386B and BWa,b for 1387B) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry. Synchronous Chip Selects (CE1, CE2, CE3 for TQFP / CE1 for BGA) and an asynchronous OE provide for easy bank selection and output three-state control. ADSP is ignored if CE1 is HIGH. Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) chip selects are all asserted active, and (3) the write signals (GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is HIGH. The address presented to the address inputs is stored into the address advancement logic and the Address Register while being presented to the memory core. The corresponding data is allowed to propagate to the input of the Output Registers. At the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within 4.2 ns (133-MHz device) if OE is active LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state, its outputs are always three-stated during the first cycle of the access. After the first cycle of the access, the outputs are controlled by the OE signal. Consecutive single read cycles are supported. The CY7C1386B/CY7C1387B are double-cycle deselect parts. Once the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals, its output will three-state immediately after the next clock rise. Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and (2) chip select is asserted active. The address presented is loaded into the address register and the address advancement logic while being delivered to the RAM core. The Write signals (GW, BWE, and BWx) and ADV inputs are ignored during this first cycle. ADSP triggered write accesses require two clock cycles to complete. If GW is asserted LOW on the second clock rise, the data presented to the DQx inputs is written into the corresponding address location in the RAM core. If GW is HIGH, then the write operation is controlled by BWE and BWx signals. The CY7C1386B/CY7C1387B provides byte Write capability that is described in the Write Cycle Description table. Asserting the Byte Write Enable input (BWE) with the selected Byte Write (BWa,b,c,d for CY7C1386B, and BWa,b for CY7C1387B) input will selectively write to only the desired bytes. Bytes not selected during a byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Because the CY7C1386B/CY7C1387B is a common I/O device, the OE must be deasserted HIGH before presenting data to the DQ inputs. Doing so will three-state the output drivers. As a safety precaution, DQ are automatically three-stated whenever a Write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC ADSC write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted HIGH, (3) chip select is asserted active, and (4) the appropriate combination of the write inputs (GW, BWE, and BWx) are asserted active to conduct a write to the desired byte(s). ADSC triggered write accesses require a single clock cycle to complete. The address presented to A[17:0] is loaded into the address register and the address advancement logic while being delivered to the RAM core. The ADV input is ignored during this cycle. If a Global Write is conducted, the data presented to the DQ[x:0] is written into the corresponding address location in the RAM core. If a byte Write is conducted, only the selected bytes are written. Bytes not selected during a byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify Write operations. Because the CY7C1386B/CY7C1387B is a common I/O device, the OE must be deasserted HIGH before presenting data to the DQ[x:0] inputs. Doing so will three-state the output drivers. As a safety precaution, DQ[x:0] are automatically three-stated whenever a write cycle is detected, regardless of the state of OE.
Burst Sequences
The CY7C1386B/CY7C1387B provides a two-bit wraparound counter, fed by A[1:0], that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel Pentium(R) applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input. Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence. Both read and write burst operations are supported.
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CY7C1386B CY7C1387B
Interleaved Burst Sequence
First Address A[1:0]] 00 01 10 11 Second Address A[1:0] 01 00 11 10 Third Address A[1:0] 10 11 00 01 Fourth Address A[1:0] 11 10 01 00 The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation "sleep" mode. Two clock cycles are required to enter into or exit from this "sleep" mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the "sleep" mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the "sleep" mode. CEs, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW.
ZZ Mode Electrical Characteristics Linear Burst Sequence
First Address A[1:0] 00 01 10 11 Sleep Mode Second Address A[1:0] 01 10 11 00 Third Address A[1:0] 10 11 00 01 Fourth Address A[1:0] 11 00 01 10 tZZREC tZZS Parameter Description IDDZZ Sleep mode standby current Device operation to ZZ ZZ recovery time Test Conditions ZZ > VDD - 0.2V Min. Max. Unit 20 mA
ZZ > VDD - 0.2V
2tCYC ns
ZZ < 0.2V
2tCYC
ns
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CY7C1386B CY7C1387B
Cycle Descriptions[1,2,3,4]
Next Cycle Unselected Unselected Unselected Unselected Unselected Begin Read Begin Read Continue Read Continue Read Continue Read Continue Read Suspend Read Suspend Read Suspend Read Suspend Read Begin Write Begin Write Begin Write Continue Write Continue Write Suspend Write Suspend Write ZZ "sleep" Add. Used None None None None None External External Next Next Next Next Current Current Current Current Current Current External Next Next Current Current None ZZ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 CE3 X H X H X L L X X X X X X X X X X L X X X X X CE2 X X L X L H H X X X X X X X X X X H X X X X X CE1 H L L L L L L X X H H X X H H X H L X H X H X ADSP X L L H H L H H H X X H H X X H X H H X H X X ADSC L X X L L X L H H H H H H H H H H L H H H H X ADV X X X X X X X L L L L H H H H H H X L L H H X OE X X X X X X X H L H L H L H L X X X X X X X X DQ Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z DQ Hi-Z DQ Hi-Z DQ Hi-Z DQ Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Write X X X X X X Read Read Read Read Read Read Read Read Read Write Write Write Write Write Write Write X
Notes: 1. X = "Don't Care." H = HIGH. L = LOW. 2. Write is defined by BWE, BWx, and GW. See Write Cycle Descriptions table. 3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 4. CE1, CE2, and CE3 are available only in the TQFP package. The BGA package has a single chip select CE1.
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CY7C1386B CY7C1387B
Write Cycle Descriptions[5,6,7]
Function (1386B) Read Read Write Byte 0 - DQa Write Byte 1- DQb Write Bytes 1, 0 Write Byte 2 - DQc Write Bytes 2, 0 Write Bytes 2, 1 Write Bytes 2, 1, 0 Write Byte 3 - DQd5 Write Bytes 3, 0 Write Bytes 3, 1 Write Bytes 3, 1, 0 Write Bytes 3, 2 Write Bytes 3, 2, 0 Write Bytes 3, 2, 1 Write All Bytes Write All Bytes GW 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 BWE 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X BWd X 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 X BWc X 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 X BWb X 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 X BWa X 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 X
Function (1387B) Read Read Write Byte 0 - DQ[7:0] and DP0 Write Byte 1 - DQ[15:8] and DP1 Write All Bytes Write All Bytes
GW 1 1 1 1 1 0
BWE 1 0 0 0 0 X
BWb X 1 1 0 0 X
BWa X 1 0 1 0 X
Notes: 5. X = "Don't Care", 1 = Logic HIGH, 0 = Logic LOW. 6. The SRAM always initiates a Read cycle when ADSP asserted, regardless of the state of GW, BWE, or BWx. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to three-state. OE is a "don't care" for the remainder of the Write cycle. 7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle DQ = High-Z when OE is inactive or when the device is deselected, and DQ = data when OE is active.
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CY7C1386B CY7C1387B
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1386B/CY7C1387B incorporates a serial boundary scan Test Access Port (TAP) in the FBGA package only. The TQFP package does not offer this functionality. This port operates in accordance with IEEE Standard 1149.1-1900, but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC standard 3.3V I/O logic levels. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a Reset state that will not interfere with the operation of the device. Test Access Port - Test Clock The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Mode Select The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) on any register. Test Data-Out (TDO) The TDO output pin is used to serially clock data-out from the registers. The e output is active depending upon the current state of the TAP state machine (see TAP Controller State Diagram). The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. Performing a TAP Reset A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a high-Z state. TAP Registers Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins as shown in the TAP Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a Reset state as described in the previous section. When the TAP controller is in the CaptureIR state, the two LSBs are loaded with a binary "01" pattern to allow for fault isolation of the board level serial test path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain states. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and output pins on the SRAM. Several no connect (NC) pins are also included in the scan register to reserve pins for higher density devices. The x36 configuration has a 70-bit-long register, and the x18 configuration has a 51-bit-long register. The boundary scan register is loaded with the contents of the RAM Input and Output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and Output ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. TAP Instruction Set Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction Code table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address, data or control signals into the Page 12 of 32
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SRAM and cannot preload the Input or Output buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; rather it performs a capture of the Inputs and Output ring when these instructions are executed. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. EXTEST EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in the TAP controller, and therefore this device is not compliant to the 1149.1 standard. The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state. SAMPLE/PRELOAD SAMPLE / PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the TAP controller is not fully 1149.1 compliant. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 10 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture set-up plus hold times (TCS and TCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. Note that since the PRELOAD part of the command is not implemented, putting the TAP into the Update to the Update-DR state while performing a SAMPLE/PRELOAD instruction will have the same effect as the Pause-DR command. Bypass When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions.
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TAP Controller State Diagram
1
TEST-LOGIC RESET
1 0 TEST-LOGIC/ IDLE 1 SELECT DR-SCAN 0 1 CAPTURE-DR 1 CAPTURE-DR 1 SELECT IR-SCAN 0
0
0
SHIFT-DR
0
SHIFT-IR
0
1 1 EXIT1-DR
1 EXIT1-IR 1
0
0
PAUSE-DR 1 0 EXIT2-DR 1
0
PAUSE-IR 1 0 EXIT2-IR 1
0
UPDATE-DR 1 0
UPDATE-IR 1 0
Note: 8. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
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TAP Controller Block Diagram
0 Bypass Register Selection Circuitry TDI Selection Circuitry TDO
2 Instruction Register
1
0
31 30
29
.
.
2
1
0
Identification Register
.
.
.
.
.
2
1
0
Boundary Scan Register
TCK TAP Controller TMS
TAP Electrical Characteristics Over the Operating Range[9, 10]
Parameter VOH1 VOH2 VOL1 VOL2 VIH VIL IX Description Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current GND VI VDDQ IOH = -4.0 mA IOH = -100 A IOL = 8.0 mA IOL = 100 A 1.7 -0.5 -5 Test Conditions Min. 2.4 VDD - 0.2 0.4 0.2 VDD + 0.3 0.7 5 Max. Unit V V V V V V A
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TAP AC Switching Characteristics Over the Operating Range[11,12]
Parameters tTCYC tTF tTH tTL Set-up Times tTMSS tTDIS tCS Hold Times tTMSH tTDIH tCH Output Times tTDOV tTDOX TCK Clock LOW to TDO Valid TCK Clock LOW to TDO Invalid 0 20 ns ns TMS Hold after TCK Clock Rise TDI Hold after Clock Rise Capture Hold after Clock Rise 10 10 10 ns ns ns TMS Set-up to TCK Clock Rise TDI Set-up to TCK Clock Rise Capture Set-up to TCK Rise 10 10 10 ns ns ns TCK Clock Cycle Time TCK Clock Frequency TCK Clock HIGH TCK Clock LOW 40 40 Description Min. 100 10 Max. Unit ns MHz ns ns
Notes: 11. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register. 12. Test conditions are specified using the load in TAP AC test conditions. TR/TF = 1 ns.
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TAP Timing and Test Conditions
1.25V 50 TDO Z0 =50 CL =20 pF 0V ALL INPUT PULSES 3.3V 1.50V
GND
(a)
tTH
tTL
Test Clock TCK
tTMSS tTMSH
tTCYC
Test Mode Select TMS
tTDIS tTDIH
Test Data-In TDI
Test Data-Out TDO
tTDOX
tTDOV
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Identification Register Definitions
Instruction Field Revision Number (31:28) Device Depth (27:23) Device Width (22:18) Cypress Device ID (17:12) Cypress JEDEC ID (11:1) ID Register Presence (0) 512K x 36 xxxx 00111 00100 xxxxx 00011100100 1 1M x 18 xxxx 01000 00011 xxxxx 00011100100 1 Description Reserved for version number. Defines depth of SRAM. 512K or 1M. Defines with of the SRAM. x36 or x18. Reserved for future use. Allows unique identification of SRAM vendor. Indicate the presence of an ID register.
Scan Register Sizes
Register Name Instruction Bypass ID Boundary Scan Bit Size (x18) 3 1 32 51 Bit Size (x36) 3 1 32 70
Identification Codes
Instruction EXTEST 000 Code Description Captures the Input/Output ring contents. Places the boundary scan register between the TDI and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant. Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. Captures the Input/Output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. Do Not Use: This instruction is reserved for future use. Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. This instruction does not implement 1149.1 preload function and is therefore not 1149.1-compliant. Do Not Use. This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operation.
IDCODE SAMPLE Z RESERVED SAMPLE/PRELOAD
001 010 011 100
RESERVED RESERVED BYPASS
101 110 111
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Boundary Scan Order (512K x 18)
Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Signal Name A A A A A A A DQa DQa DQa DQa DQa DQa DQa DQa DQa ZZ DQb DQb DQb DQb DQb DQb DQb DQb DQb A A ADV# ADSP# ADSC# OE# BWE# GW# CLK Bump ID 2R 3T 4T 5T 6R 3B 5B 6P 7N 6M 7L 6K 7P 6N 6L 7K 7T 6H 7G 6F 7E 6D 7H 6G 6E 7D 6A 5A 4G 4A 4B 4F 4M 4H 4K Bit # 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 A BWa# BWb# BWc# BWd# A CE# A A DQc DQc DQc DQc DQc DQc DQc DQc DQc NC DQd DQd DQd DQd DQd DQd DQd DQd DQd MODE A A A A A1 A0 Signal Name Bump ID 6B 5L 5G 3G 3L 2B 4E 3A 2A 2D 1E 2F 1G 1D 1D 2E 2G 1H 5R 2K 1L 2M 1N 2P 1K 2L 2N 1P 3R 2C 3C 5C 6C 4N 4P
Boundary Scan Order (1M x 18)
Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Signal Name A A A A A A A DQa DQa DQa DQa ZZ DQa DQa DQa DQa DQa A A A ADV# ADSP# ADSC# OE# BWE# GW# CLK A BWa# BWb# A CE# A A DQb Bump ID 2R 2T 3T 5T 6R 3B 5B 7P 6N 6L 7K 7T 6H 7G 6F 7E 6D 6T 6A 5A 4G 4A 4B 4F 4M 4H 4K 6B 5L 3G 2B 4E 3A 2A 1D Bit # 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 Signal Name DQb DQb DQb NC DQb DQb DQb DQb DQb MODE A A A A A1 A0 Bump ID 2E 2G 1H 5R 2K 1L 2M 1N 2P 3R 2C 3C 5C 6C 4N 4P
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................-55C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VDD Relative to GND ....... -0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State[13] ............................... -0.5V to VDDQ + 0.5V DC Input Voltage[13] ............................ -0.5V to VDDQ + 0.5V Current into Outputs (LOW) .........................................20 mA Electrical Characteristics Over the Operating Range Parameter VDD VDDQ VOH VOL VIH VIL IX Description Power Supply Voltage I/O Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[13] Input Load Current Input Current of MODE Input Current of ZZ IOZ IDD Output Leakage Current VDD Operating Supply Input = VSS GND < VI < VDDQ, Output Disabled VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC 5.0-ns cycle, 200 MHz 6.0-ns cycle, 167 MHz 6.7-ns cycle, 150 MHz 7.5-ns cycle, 133 MHz ISB1 Automatic CE Power-Down Current--TTL Inputs Max. VDD, Device Deselected, VIN > VIH or VIN VDDQ - 0.3V, f = 0 Max. VDD, Device Deselected, or VIN 0.3V or VIN > VDDQ - 0.3V f = fMAX = 1/tCYC Max. VDD, Device Deselected, VIN VIH or VIN VIL, f = 0 5.0-ns cycle, 200 MHz 6.0-ns cycle, 167 MHz 6.7-ns cycle, 150 MHz 7.5-ns cycle, 133 MHz ISB2 Automatic CE Power-Down Current--CMOS Inputs Automatic CE Power-Down Current--CMOS Inputs All speed grades GND < VI < VDDQ -30 -30 3.3V range 3.3V range 2.5V range VDD = Min., IOH = -4.0 mA VDD = Min., IOH = -1.0 mA VDD = Min., IOL = 8.0 mA VDD = Min., IOH = 1.0 mA 3.3V 2.5V 3.3V 2.5V 3.3 V 2.5V 3.3V 2.5V 2.0 1.7 -0.3 -0.3 0.8 0.7 5 30 30 5 315 285 265 245 140 120 110 105 20 Static Discharge Voltage .......................................... >1500V (per MIL-STD-883, Method 3015) Latch-Up Current ................................................... >200 m A
Operating Range
Range Commercial Industrial Ambient Temp.[14.] 0C to +70C -40C to +85C VDD 3.3V -5%/+10% VDDQ 2.5V -5% 3.3V + 10%
Test Conditions
Min. 3.135 2.375 2.375 2.4 2.0
Max. 3.63 3.63 VDD
Unit V V V V V
0.4 0.4
V V V V V V A A A A mA mA mA mA mA mA mA mA mA
ISB3
5.0-ns cycle, 200 MHz 6.0-ns cycle, 167 MHz 6.7-ns cycle, 150 MHz 7.5-ns cycle, 133 MHz All Speeds
110 100 90 85 50
mA mA mA mA mA
ISB4
Automatic CS Power-Down Current--TTL Inputs
Notes: 13. Minimum voltage equals -2.0V for pulse durations of less than 20 ns 14. TA is the temperature.
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Capacitance[15]
Parameter CIN CCLK CI/O Description Input Capacitance Clock Input Capacitance Input/Output Capacitance Test Conditions TA = 25C, f = 1 MHz VDD = 3.3V VDDQ = 3.3 Max. 3 3 3 Unit pF pF pF
AC Test Loads and Waveforms[16]
OUTPUT Z0 = 50 RL = 50 VTH = 1.5V VDDQ OUTPUT 5 pF R = 351 INCLUDING JIG AND SCOPE R = 317 ALL INPUT PULSES 3.0V 10% GND 90%
[16]
90% 10%
1 V/ns
1 V/ns
(a)
(b)
(c)
Thermal Resistance[15]
Description 119 BGA 165 FBGA 100-pin TQFP Test Conditions Still Air, soldered on a 114.3 x 101.6 x 1.57 mm3, 2-layer board Still Air, soldered on a 4.25 x 1.125 inch, 4-layer printed circuit board QJA (Junction to Ambient) 41.54 44.51 25 QJC (Junction to Case) 6.33 2.38 9 Units C/W C/W C/W
Notes: 15. Tested initially and after any design or process changes that may affect these parameters. 16. Input waveform should have a slew rate of 1 V/ns.
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Switching Characteristics Over the Operating Range[17,18,19]
-200 Parameter tCYC tCH tCL tAS tAH tCO tDOH tADS tADH tWES tWEH tADVS tADVH tDS tDH tCES tCEH tCHZ tCLZ tEOHZ tEOLZ tEOV Clock HIGH Clock LOW Address Set-Up Before CLK Rise Address Hold After CLK Rise Data Output Valid After CLK Rise Data Output Hold After CLK Rise ADSP, ADSC Set-Up Before CLK Rise ADSP, ADSC Hold After CLK Rise BWE, GW, BWx Set-Up Before CLK Rise BWE, GW, BWx Hold After CLK Rise ADV Set-Up Before CLK Rise ADV Hold After CLK Rise Data Input Set-Up Before CLK Rise Data Input Hold After CLK Rise Chip enable Set-Up Chip enable Hold After CLK Rise Clock to High-Z
[18]
-167 Min. 6.0 2.1 2.1 1.5 0.5 Max.
-150 Min. 6.7 2.3 2.3 1.5 0.5 Max.
-133 Min. 7.5 2.5 2.5 1.5 0.5 Max. Unit ns ns ns ns ns 4.2 1.5 1.5 0.5 1.5 0.5 1.5 0.5 1.5 0.5 1.5 0.5 ns ns ns ns ns ns ns ns ns ns ns ns 3.0 1.3 4.0 0 4.2 ns ns ns ns ns
Description Clock Cycle Time
Min. 5.0 1.8 1.8 1.4 0.4
Max.
3.0 1.5 1.4 0.4 1.4 0.4 1.4 0.4 1.4 0.4 1.4 0.4 3.0 1.3 1.3 4.0 0 3.0 0 1.5 1.5 0.5 1.5 0.5 1.5 0.5 1.5 0.5 1.5 0.5
3.4 1.5 1.5 0.5 1.5 0.5 1.5 0.5 1.5 0.5 1.5 0.5 3.0 1.3 4.0 0 3.4
3.8
3.0 4.0 3.8
Clock to Low-Z[18] OE HIGH to Output High-Z OE LOW to Output Valid
[18,19]
OE LOW to Output Low-Z[18,19]
[18]
Notes: 17. Unless otherwise noted, test conditions assume signal transition time of 2.5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and load capacitance. Shown in (a), (b), and (c) of AC test loads. 18. tCHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with a load capacitance of 5 pF as in part (b) of AC test loads. Transition is measured 200 mV from steady-state voltage. 19. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ.
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CY7C1386B CY7C1387B
1
Switching Waveforms
Write Cycle Timing[4,20,21]
Single Write tCH tCYC CLK tADH tADS ADSP tADS ADSC tADVS ADV tAS ADD WD1 tAH GW tWS BWE tCES CE1 tCES CE2 tCEH tCEH tWH tWS tADVH tADH tCL
Burst Write
Pipelined Write Unselected
ADSP ignored with CE1 inactive
ADSC initiated Write
ADV must be inactive for ADSP Write WD2 WD3
tWH
CE1 masks ADSP
Unselected with CE2
CE3 tCES OE tDS Data In High-Z 1a 1a 2a = Undefined 2b 2c = Don't Care 2d 3a High-Z tCEH tDH
Notes: 20. WE is the combination of BWE, BWx, and GW to define a Write cycle (see Write cycle descriptions table). 21. WDx stands for Write Data to Address X.
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Switching Waveforms (continued)
Read Cycle Timing[4,20,22]
Single Read tCYC CLK tADS ADSP tADS ADSC tADVS ADV tAS ADD RD1 tAH GW tWS tWH BWE tCES CE1 tCEH tADVH RD2 tADH tADH tCL tCH
Burst Read Pipelined Read
Unselected
ADSP ignored with CE1 inactive
ADSC initiated Read
Suspend Burst
RD3
tWS
tWH
CE1 masks ADSP
Unselected with CE2 CE2 tCES CE3 tCES tCEH OE tEOV tOEHZ tDOH Data Out tCO 1a 1a tCLZ = Don't Care
Note: 22. RDx stands for Read Data from Address X.
tCEH
Double-Cycle Deselect 2b 2c 2c 2d 3a tCHZ = Undefined
2a
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CY7C1386B CY7C1387B
Switching Waveforms (continued)
Read/Write Cycle Timing[4,20,21,22]
Single Read tCYC
Single Write tCH
Burst Read Pipelined Read
Unselected
CLK tADS ADSP tADS ADSC tADVS ADV tAS ADD RD1 tAH GW tWS tWH BWE tCES CE1 tCEH tWH CE1 masks ADSP tADVH WD2 RD3 tADH tADH tCL ADSP ignored with CE1 inactive
tWS
CE2 tCES CE3 tCES tCEH OE tEOHZ tEOLZ tCO tDS 2a Out 3a Out tDH 3b Out 3c Out tDOH 3d Out tCHZ Double-Cycle Deselect tEOV tCEH
Data In/Out
1a 1a Out
2a In
= Don't Care
= Undefined
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CY7C1386B CY7C1387B
Switching Waveforms (continued)
Pipeline Timing[4,23;24]
tCH CLK tCYC tCL
tAS ADD RD1 tADS ADSC ADSP initiated Reads ADSP RD2 RD3 RD4 tADH WD1 WD2 WD3 WD4
ADSC initiated Reads
ADV tCES CE1 tCEH
CE tWES BWE ADSP ignored with CE1 HIGH tWEH
OE
tCLZ Data In/Out tCDV Back-to-Back Reads = Don't Care = Undefined tDOH tCHZ 1a Out 2a Out 3a Out 4a Out 1a In 2a In 3a In 4a D(C) In
Notes: 23. Device originally deselected. 24. CE is the combination of CE2 and CE3. All chip selects need to be active in order to select the device.
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Switching Waveforms (continued)
OE Switching Waveforms
OE tEOHZ I/Os Three-State tEOV
tEOLZ
ZZ Mode Timing [4,25,26]
CLK
ADSP HIGH ADSC
CE1
CE2
LOW
HIGH CE3
ZZ tZZS
IDD
IDD(active) tZZREC IDDZZ Three-state
I/Os
Note: 25. Device must be deselected when entering ZZ mode. See Cycle Descriptions Table for all possible signal conditions to deselect the device. 26. I/Os are in three-state when exiting ZZ sleep mode.
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Ordering Information
Speed (MHz) 200 167 150 133 200 167 150 133 200 167 150 133 200 167 150 133 200 167 150 133 200 167 150 133 167 150 133 167 150 133 167 150 133 167 150 133 167 150 133 167 150 133 Ordering Code CY7C1386B-200AC CY7C1386B-167AC CY7C1386B-150AC CY7C1386B-133AC CY7C1387B-200AC -167AC -150AC -133AC CY7C1386B-200BGC CY7C1386B-167BGC CY7C1386B-150BGC CY7C1386B-133BGC CY7C1387B-200BGC -167BGC -150BGC -133BGC CY7C1386B-200BZC CY7C1386B-167BZC CY7C1386B-150BZC CY7C1386B-133BZC CY7C1387B-200BZC -167BZC -150BZC -133BZC CY7C1386B-167AI CY7C1386B-150AI CY7C1386B-133AI -167AI -150AI -133AI CY7C1386B-167BGI CY7C1386B-150BGI CY7C1386B-133BGI -167BGI -150BGI -133BGI CY7C1386B-167BZI CY7C1386B-150BZI CY7C1386B-133BZI -167BZI -150BZI -133BZI BB165A 165 FBGA BG119 119 BGA A101 100-Lead Thin Quad Flat Pack Industrial BB165A 165 FBGA BG119 119 BGA Package Name A101 Package Type 100-Lead Thin Quad Flat Pack Operating Range Commercial
Shaded areas contain advance information.
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CY7C1386B CY7C1387B
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm)
51-85050-A
Document #: 38-05195 Rev. **
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CY7C1386B CY7C1387B
Package Diagrams (continued)
119-Ball BGA (14 x 22 x 2.4 mm)
Document #: 38-05195 Rev. **
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CY7C1386B CY7C1387B
Package Diagrams (continued)
165-Ball FBGA (13 x 15 x 1.2 mm) BB165A
Document #: 38-05195 Rev. **
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(c) Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1386B CY7C1387B
Revision History
Document Title: CY7C1386B/CY7C1387B 512K x 36/1M x 18 Pipelined DCD SRAM Document Number:38-05195 REV. ** ECN NO. 112030 ISSUE DATE 12/09/01 ORIG. OF CHANGE DSG DESCRIPTION OF CHANGE Change from Spec number: 38-01117 to 38-05195
Document #: 38-05195 Rev. **
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